TAIPEI (TVBS News) — MediaTek (聯發科) said Monday (Aug. 31) that panel-level fan-out packaging could cut chip packaging costs by about 30%. The Taiwanese chipmaker made the announcement as artificial intelligence drives demand for larger processors that exceed conventional wafer-level manufacturing limits.
MediaTek Senior Director Jonas Hsu (徐潤忠) spoke at the Panel-Level Fan-Out Packaging Innovation Forum (面板級扇出型封裝創新論壇) at SEMICON Taiwan. He compared the shift to replacing a round pizza with a rectangular one. The larger format allows manufacturers to fit more chips per run while reducing wasted edge space, Hsu said.
Traditional 12-inch wafers leave significant unused space around the edges when accommodating large rectangular chips. Rectangular panels measuring 510×515 mm or 600×600 mm offer at least 3.7 times the usable area of a 12-inch wafer. The approach could increase output per production run by about 78%, Hsu said.
Advanced AI chip packaging now reaches 3.5 to four times the standard reticle size, reducing wafer utilization, MediaTek said. Tight capacity for TSMC's Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging and high expansion costs have increased industry interest in panel-level manufacturing. MediaTek said potential packaging cost reductions could reach around 30%.
MediaTek has worked on panel-level fan-out packaging for more than seven years, Hsu said. The company's first product took three years to reach mass production. Annual output is now approaching the equivalent of 1 million 8-inch wafers, with yields comparable to wafer-level packaging.
Panel-level packaging is not intended to fully replace wafer-level packaging, Hsu stressed. Manufacturers should choose the most suitable platform based on product design and manufacturability. ◼
