Powertech Technology (6239.TW) has spent nearly three decades as the world's largest memory packaging and testing company. Now, as advanced packaging becomes the tightest bottleneck in the AI supply chain, Powertech is positioning itself as the credible alternative to TSMC's CoWoS platform. With a proprietary glass-substrate technology that rivals TSMC at significantly lower cost, Powertech has gone from quiet memory specialist to one of the most strategically important companies in the AI chip ecosystem.
Powertech entered 2026 with strong momentum. February revenue reached NT$7.24 billion (US$227 million), up 43% year on year, making it the second-largest OSAT firm by monthly revenue behind ASE. March revenue growth remained robust at roughly 39% year on year. Q4 2025 quarterly revenue hit NT$21.41 billion (US$681 million), up 25.2% year on year, with packaging utilization climbing above 90% and testing utilization reaching 85%. Net income rose 22.3% to NT$1.86 billion (US$59 million), the company's strongest quarterly profit in three years. Management expects high double-digit year-on-year growth to continue through the first half of 2026, driven by rising demand for both memory packaging and advanced AI chip packaging.
Powertech is backing its technology ambitions with NT$44.3 billion (US$1.4 billion) in capital expenditure over three years, the largest investment program in the company's history. The spending is concentrated on two facilities. The P11 plant in Hsinchu, its main production base for fan-out panel-level packaging, is undergoing cleanroom expansion scheduled for completion by mid-2026, with a target monthly capacity of 6,000 panels. The P12 plant, converted from a former AUO display factory acquired for NT$6.9 billion (US$221 million), will add AI chip packaging using ABF substrates and provide additional space for research and development.
Powertech employs more than 18,000 workers across Taiwan, China, and Japan, and maintains close partnerships with major memory manufacturers including Micron Technology, which reportedly outsources a majority of its DRAM packaging and testing to the company.
After solving key challenges including panel warpage, Powertech is targeting yield rates of 95 to 98%. Full customer qualification is expected by end of 2026, with volume production beginning in the first half of 2027. The company has finalized a 510mm by 515mm panel standard approved by multiple customers and is installing equipment capable of processing packages up to five times reticle size.
Powertech is also developing co-packaged optics (CPO) for AI chips, a technology that brings data transmission components closer to the processor. CPO is expected to enter mass production by late 2027.
Powertech's trajectory for the rest of 2026 hinges on two milestones. The first is completing PiFO customer qualification, which would validate glass-based fan-out as a genuine second source to TSMC's CoWoS-L and open the door to volume production in 2027. The second is sustaining growth in its core memory packaging business as demand for high-bandwidth memory surges alongside the Nvidia Rubin ramp and custom ASIC proliferation from the major hyperscalers.
The broader picture favors Powertech. With TSMC's advanced packaging fully booked and demand growing at an 80% annual compound rate, the industry urgently needs credible alternatives. Powertech's combination of proven memory expertise, a decade of PiFO investment, and US$1.4 billion in committed capex positions it to capture meaningful share of a market expanding far faster than any single supplier can serve.