At its 2026 North America Technology Symposium, TSMC unveiled a roadmap that highlights where the world’s largest contract chipmaker is placing its boldest bets and where it is choosing restraint.
The semiconductor giant plans to open an advanced chip packaging facility in Arizona by 2029, even as it signals it will further optimize existing manufacturing processes before adopting next-generation high-NA EUV lithography machines from ASML.
The announcements reflect a deeper strategic shift now reshaping the semiconductor industry: advanced packaging, the art of integrating multiple chips into powerful, high-performance modules, is becoming just as critical as transistor fabrication itself, especially for artificial intelligence workloads.
TSMC has already broken ground on packaging capabilities at its Arizona campus. Kevin Zhang, deputy co-chief operating officer, told reporters the company is “aggressively expanding” CoWoS and 3D-IC packaging technologies, with initial production targeted before 2029. TSMC is also working closely with partner Amkor Technology to accelerate the rollout.
TSMC executives noted that its first Arizona fab is already achieving yields comparable to its Taiwan facilities, with a second fab scheduled to begin production next year.
On the lithography front, TSMC is taking a more measured approach, indicating that it has no plans to deploy ASML’s high-numerical-aperture extreme ultraviolet (high-NA EUV) machines in high-volume production through at least 2029. Existing EUV systems remain sufficient for TSMC's roadmap, and the company is pursuing alternative design techniques and process optimizations to deliver continued performance improvements at a more sustainable cost.
Under the symposium theme “Expanding AI with Leadership Silicon,” TSMC introduced its A13 process node, the successor to the A14 technology introduced in 2025. A13 shrinks chip area by 6% while preserving full design-rule backward compatibility, easing customer migration to TSMC’s nanosheet transistor architecture. Production is slated for 2029. The company also previewed A12, which adds backside power delivery, a key feature for AI and high-performance computing, and extended its N2 family with the N2U variant, targeting 2028 volume production.
Packaging technologies received equal emphasis. TSMC is scaling its CoWoS platform, expanding it to 14 times reticle size by 2028. This will enable packages integrating roughly 10 compute dies and 20 high-bandwidth memory (HBM) stacks. An even larger configuration is slated for 2029, alongside a 40x-reticle System-on-Wafer solution. The company also confirmed that its co-packaged optics technology, which promises to to double power efficiency and slash data-center latency by up to 90%, remains on track for production in 2026.
TSMC's ambitious capacity expansion combined with disciplined restraint on tools reflects a semiconductor industry being reshaped by AI demand and the need to address evolving customer supply chain needs. Leading-edge fabs alone no longer define competitive advantage; packaging, supply-chain geography, and cost control now matter just as much. For US customers racing to build the next generation of AI systems, TSMC's Arizona build-out may prove as consequential as any single process-node breakthrough.