CoPoS takes shape as Taiwan advances panel-level packaging

Growing AI packages are increasing interest in CoPoS and other panel-level packaging technologies. As designers combine more processing chips and high-bandwidth memory stacks, the structures connecting them occupy more space. Square or rectangular processing panels can accommodate these structures with less wasted area than circular wafers, potentially increasing output and reducing costs.

Taiwan’s manufacturers are pursuing several approaches. TSMC is developing CoPoS, while ASE and Powertech are advancing fan-out panel-level packaging, which extends electrical connections beyond individual chips. Innolux is adapting its display-manufacturing expertise to the same market. Their technologies differ in wiring density, assembly sequence, and target applications.

CoPoS, short for Chip-on-Panel-on-Substrate, extends TSMC’s packaging capabilities beyond CoWoS, or Chip-on-Wafer-on-Substrate. CoWoS connects processors and memory through dense wiring structures mounted on a package substrate. CoPoS moves relevant packaging operations onto panels; the chips themselves continue to be fabricated on wafers.

TSMC’s October earnings call provided an important reminder that this transition will take time. Chairman C.C. Wei said the company was developing CoPoS to reduce future costs, while CoWoS remained customers’ first choice. In April, he had confirmed construction of a pilot line, with production expected a couple of years later.

ASE is moving toward production with an automated 310-by-310-millimeter line supporting its FOCoS (Fan-Out Chip-on-Substrate ) and FOCoS-Bridge platforms. An August update targeted production by the first quarter of 2027. Preserving existing design rules could help customers move suitable products from wafer processing to panels without fundamentally redesigning their packages.

Powertech reaffirmed its 2027 production target in October, with customer qualification continuing for its 510-by-515-millimeter platform. Its portfolio includes chip-first, chip-middle and chip-last processes. Chip-last builds and checks the redistribution wiring before attaching chips, reducing the risk of losing expensive silicon to defective connections.

Innolux introduced a chip-last platform in September using its Heterogeneous Integration Panel on Substrate, or HIPoS, architecture. It combines multilayer wiring with an embedded core on 620-by-670-millimeter panels. Customer qualification is the next step, with mass production targeted for the second half of 2027. Its experience processing large display panels provides manufacturing and automation expertise for this transition.

Larger surfaces also create manufacturing challenges. Equipment must maintain precise alignment and uniform processing across the panel, while materials must resist warpage that can disrupt patterning and bonding. Better space utilization produces savings only when yields and processing costs support it.

The emerging competition therefore concerns how reliably and economically each supplier can manufacture a customer’s package. CoPoS adds another option to TSMC’s portfolio, while ASE, Powertech, and Innolux give customers more routes to panel production. Their progress through qualification and into volume manufacturing will determine how quickly those options become commercially significant.